1. Technical Field
The present invention relates generally to an improved data processing system and in particular to a method and apparatus for processing interrupts. Still more particularly, the present invention relates to a method and apparatus for processing hardware interrupts in a data processing system.
2. Description of the Related Art
An interrupt is a request-for-attention signal that can be passed by either hardware or software to a computer's processor. An interrupt, sometimes called a "trap", causes the processor to suspend its current operations, save the status of its work, and transfer control to a special routine, known as an interrupt handler, which causes a particular set of instructions to be carried out. Interrupts can occur for many reasons ranging from normal to highly abnormal. These reasons can include service requests from various hardware devices, errors in processing, program attempts to do the impossible, memory problems, and imminent failure of some vital component. When a processor receives interrupt requests from more than one source, a hierarchy of "permission" levels called interrupt priorities determines which of the interrupts is handled first. Many operating-system functions such as opening files, reading from files, and closing them can be accessed through interrupts. By using interrupts, a program can communicate with the operating system.
Interrupts are the processor's means of communicating with the other elements that make up a computer system. If a constant stream of interrupt requests would disrupt or complicate processing at a critical point, a program can temporarily disable interrupts, effectively gaining sole control of the processor's attention for the time needed.
With a peripheral component interconnect (PCI) bus, processors in components such as chips, boards, and other subsystems process interrupts on a level sensitive mode. In the case of a level sensitive mode, also referred to as a level trigger, an interrupt is requested when the interrupt signal is in a low level state or a high level state. On a PCI bus, multiple components can share an interrupt line. When a hardware interrupt occurs, the PCI bus/host processor is required to service this interrupt before the shared hardware interrupt can be used by another part of the data processing system. This type of hardware interrupt handling locks the interrupt service routing to just one interrupt, if the interrupt begins as a hardware interrupt.
This type of situation can reduce the speed and efficiency of the data processing system because other interrupts cannot be handled until the hardware interrupt has been processed by the particular chip or device receiving the interrupt. As additional components are added to the data processing system, the speed and efficiency can be reduced even further. Therefore, it would be advantageous to have an improved method and apparatus for processing hardware interrupts occurring in a data processing system in which multiple components share an interrupt line.